1. Field
Embodiments described herein generally relate to the field of semiconductor manufacturing processes and devices. More particularly, the embodiments described herein are related to the selective removal of nitrogen from the nitrided areas of a substrate.
2. Description of the Related Art
As semiconductor devices continue to scale down according to Moore's Law, processing challenges develop. One such challenge arises in floating gate (FG) NAND flash memory chips, which feature transistors that incorporate two gate elements, a control gate (CG) and a floating gate (FG), to enable each transistor to assume more than one bit value. FG NAND memory forms the basis of most USB flash memory devices and memory card formats used today.
As critical dimensions of FG NAND devices shrink, the geometry of the various components becomes more challenging for manufacturers. Aspect ratios rise and uniformity, tolerance, and reliability issues proliferate. With NAND flash memory increasing in popularity as a convenient storage medium, there is a need for improved manufacturing processes to overcome scaling challenges particular to NAND flash devices.
The NAND flash floating gate (FG) memory cell is comprised of a thick tunnel oxide (TO), a polysilicon FG, an inter-poly dielectric (IPD) and a control gate (CG). The poly FG is isolated from the channel by the TO and from the CG by the IPD. A program/erase (P/E) operation is used to set the memory state of the device. During the program operation a positive voltage is applied to the CG, injecting electrons from the channel into the FG. The stored electrons shift the threshold voltage (Vt) of the transistor, indicating the “0” state. During the erase operation a negative voltage is applied to the CG to expel the stored electrons from the floating gate into the channel, resetting the Vt to the “1” state.
The difference between the program Vt and erase Vt is referred to as the memory window and is a key device parameter defining the range of operation. At all other times, the memory cell is in retention mode, where the cell terminals are grounded. The FG should retain the stored charge for at least 10 years. However, charge loss can occur when electrons leak through defects in the dielectric films (either TO or IPD) surrounding the FG, causing a Vt shift that will eventually compromise the identification (read-out) of the memory state. Therefore, retention of the FG charge is a key requirement for reliable operation.
Meeting device reliability requirements becomes more difficult with the physical scaling of the FG array. At each technology node, the number of electrons stored in the FG decreases from, for example, approximately 1,000 electrons at the 90 nm node to ˜100 electrons at the 30 nm node. Therefore, the impact on Vt for each electron lost from the FG will be much greater at 30 nm than at 90 nm. One consequence of this has been that the TO thickness has not been reduced with device scaling and has even increased in thickness slightly to improve charge retention.
Another challenge is the scaling of the IPD film stack thickness—typically from 150 Å at the 50 nm node to 125 Å at the 30 nm node. This results in a corresponding reduction in equivalent oxide thickness (EOT), or capacitance, a change that is required to maintain good electrical coupling between the CG and FG. However, as the thickness of the IPD stack is reduced, leakage from the FG is more likely to occur. Hence, improvements in the IPD electrical properties are essential to limit leakage with continued scaling.
To enable continued physical and electrical scaling of the flash device, nitridation techniques such as plasma nitridation can be used to improve the properties of the TO, bottom IPD, and top IPD layers of a floating gate memory cell structure. However, nitridation processes are often difficult to control leading to incorporation of nitrogen in unwanted areas.
Thus, there is a need for improved methods for nitridation of stacks of materials.